The present invention relates generally to methods of resetting or erasing amorphous memory devices and more specifically to an improved method of resetting or erasing amorphous devices while minimizing electromigration.
Amorphous semiconductor memory devices, for example a tellurium based chalcogenide glass, are well known. These memory devices are generally bistable devices, the film of memory semiconductor material is capable of being switched from a stable high resistance condition into a stable low resistance condition when a write or set voltage pulse of relatively long duration (e.g., 1/2-100 milliseconds or more) is applied. Such a set voltage pulse causes current to flow in a small filament (generally under 10 microns in diameter). The set or write current pulse generally heats regions of the semiconductor material above its glass transition and to its crystallization temperature. The consequence is that the material crystallizes around and in the region of the conducting filament. Set current pulses are commonly of a value of from 0.5 milliamperes to about 15 milliamperes, although they are generally well under 10 milliamperes for most memory applications. The magnitude of the set current pulse is determined by the open circuit amplitude of the set voltage pulse and the total series circuit resistance involved including the memory device. A crystallized low resistance filament remains indefinitely, even when the applied voltage and current are removed, until reset or erased to its initial amorphous high resistance condition.
The set crystallized filament in the semiconductor materials can generally be erased or reset by applying one or more reset current pulses of relatively short duration, such current pulses are of the order of 10 microseconds duration. The reset or erase current pulses heat the entire filament of the semiconductor material to a temperature above the crystallization and melting temperatures of the material. In this condition, the crystalline filament is melted or otherwise reformed into the original amorphous mass. When such a reset current pulse is terminated, the material quickly cools and leaves a generally amorphous composition like the original one. Sometimes, it takes a number of reset current pulses to convert a previous set filament to what appears to be a fully reset state.
While the resistance and threshold voltage values of a reset filament region may indicate it has apparently been fully reset to its original amorphous composition (except for some non-resettable crystallites which ensure that subsequent crystalline filaments are formed in the same place), the reset filament region often is non-homogeneous, with the crystallizable elements like tellurium in various degrees of concentration. This produces threshold voltage degredation when the device is stored at elevated temperatures because the materials rich in tellurium crystalize at low temperatures.
This problem has been partially overcome by feeding a number of additional reset current pulses through an apparently fully reset filament region, which further homogenizes the region, as disclosed in U.S. Pat. No. 3,846,767. This patent describes a reset procedure utilizing eight, 150 milliamperes reset current pulses spaced apart 100 microseconds. The use of such high reset current pulses to reset and homogenize the memory semiconductor material of memory devices severly limits the practical applications of memory devices in memory arrays where cost and size restrictions require high packing densities having maximum current ratings of under 50 milliamperes and sometimes under 10 milliamperes. Thus, it becomes of great importance to be able to reliably reset a memory device used in such memory arrays with reset current pulses of under 50 milliamperes, and preferably under 10 milliamperes.
These additional current pulses, while solving one problem, introduce a second. This second problem is the reduction of the write/erase lifetime on the number of write/erase cycles before the threshold voltage of the device has reduced below an acceptable level (i.e., the device fails).
This threshold degradation is caused in a germanium-tellurium memory semiconductor composition by electromigration of tellurium during the flow of reset current. The degree of which degradation is directly related to the current density involved. Such electromigration of tellurium builds up a progressively greater thickness of crystalline tellurium next to one of the electrodes involved, which progressively reduces the threshold voltage value of the memory switch device.
U.S. Pat. No. 3,875,566 discloses that amorphous devices could be erased by the use of a burst of a large number of reset current pulses each of an amplitude which was believed to be only a small fraction of the amplitude thought necessary to effect resetting of the entire filamentous path. The reset current pulses used in the practice of this resetting technique were generated by a constant current source clamped at a voltage limited to a value below the threshold voltage of the fully reset memory device. This technique acts so as to stablize the threshold voltage values of all the memory switch devices to which the current source was applied at identical or near identical values, despite the somewhat varying threshold voltage values of the various particular memory devices of the array. Since the threshold voltage valve of a filament being progressively reset gradually increases with the degree of reset achieved, when the threshold voltage value of the partially reset filament of the memory device being reset exceeds the maximum possible voltage output of the constant current reset source, purposefully set below the maximum possible value thereof, the memory switch device cannot be rendered conductive by any subsequently generated reset voltage pulses, and so no further reset action is possible. It is not then possible to effect the maximum degree of rehomogenization of the filament region since under this reset procedure the device is never fully reset and does not receive reset current pulses which homogenize a fully reset filament.
U.S. Pat. No. 3,886,577 attempts to stablize threshold voltage of a filament type memory device by providing adjacent the positive electrode a substantially enrichment of tellurium in a germanium-tellurium composition. The initial enrichment with tellurium of the area next to the positive electrode reduces the number of set and reset cycles to achieve what was thought to be a stable equilibrium of electromigration and diffusion. While an advantageous initial threshold stablization was achieved in a few set and reset cycles, it was subsequently discovered that the threshold voltage stablization observed did not in fact continue indefinitely.
U.S. Pat. No. 3,922,648 discloses a resetting method comprising a burst of reset current pulses at least in the neighborhood of about 10 pulses. Each pulse is substantially under 10 microseconds in duration and the pulses in each burst are spaced apart substantially under 10 microseconds, which is less than two and preferably of the order of one thermal time constant or less of the device, so that the filament region involved does not substantially completely cool to ambient temperature between reset pulses, but rather reaches a temperature intermediate the reset and ambient temperatures. The patent theorized that threshold degradation is due to an imbalance between electromigration of tellurium during flow of reset current and diffusion thereof in the other direction between reset pulses. For reset current pulses spaced apart less than than the thermal time constant of the amorphous semiconductor film involved, the filament region is still hot when the next reset pulse arrives. Consequently, an area of higher conductivity exists which results in a lower maximum current density and reduced electromigration. With such reduced electromigration, the diffusion which exists after termination of each reset pulse balances out the amount of electromigration during the flow of reset current. In such case, the intial low amplitude reset current pulses fully reset the filament path and the following low amplitude reset current pulses homogenize the filament path.
While the method of this patent minimizes current spikes from the threshold switching that occur on each erase pulse, it does not provide the most effective erase. Neither does it remove two other causes of electromigration. Namely the overdriving occurring on the first pulse of an erase sequence and the overdriving occurring from localization of current after switching, while adding the burden of maintaining precision in the timing of the erase pulse spacing. A model of a device operating according to the method of U.S. Pat. No. 3,922,648 is illustrated in FIG. 1A, B and C. A semiconductor substrate includes a semiconductor amorphous device 10 which is illustrated in FIG. 1A as including a crystalline, ordered filament 12. Path 13 is the region where initial maximum current density is realized. On application of the reset pulse, the filament 12 is heated to above the phase change temperature and the crystals returned to the amorphous state at a melt or revitrifying temperature as illustrated in FIG. 1B as 14. As the filament 12 cools, the area 14 contracts axially and radially. This is illustrated in FIG. 1C. The cooled area is basically converted back to an amorphous material 16 having small localized crystalline 18 therein. Using the appropriately spaced pulses of the sequence of the patent, the area 14 in FIG. 1C is never allowed to disappear until the end of the sequence. Thus during the subsequent erase pulses in the sequence, area 14 expands axially and radially. As stated previously, this technique does not eliminate overdrive along a preferred path or of the whole crystal filament on the first pulse of sequence nor during localization after switching of subsequent pulses.
Thus there exists a need of a method of resetting amorphous memory devices which minimizes electromigration addressing all three overdriving causes thereof while providing the practical advantages of low current and an independence from timing constraints.
In our application titled "Multilevel Erase Pulse for Amorphous Memory Devices", filed simultaneously with the present application, a single multilevel erase pulse is disclosed as an optimum single pulse to minimize electromigration over the whole erase sequence. Since the single pulse included high and low level current amplitudes for the first as well as the last pulse in the sequence, overdrive is present during the later pulses in the sequence. Although it reduces electromigration and extends the erase/write lifetime of amorphous memory devices, additional minimizing of electromigration is desirable.